DRAM Access Simulator

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Model DRAM command timing (PRE / RAS / CAS) under an open-row or closed-row policy, across multiple banks. Set the timing parameters from a spec sheet, describe an access sequence (e.g. a row-buffer miss followed by four row hits), and step through the resulting command schedule.

Timing Parameters (defaults: DDR3-1333)

t_CK — clock cycle (ns) t_RP — precharge (cycles) t_RCD — activate (cycles) CL — CAS read latency (cycles) WL — CAS write latency (cycles) BL — burst length (columns) t_WTR — write to read (cycles) t_WR — write recovery (cycles) t_RRD — activate to activate (cycles) t_FAW — four activate window (cycles) t_RFC — refresh to activate (nsec) t_REFI — refresh interval (µsec)

t_WTR, t_WR, t_RFC and t_REFI are shown for reference and are not injected into the command schedule below (no periodic refresh is modeled; write recovery is approximated by waiting a full CL/WL before precharge).

Policy & Topology

Row buffer policy Number of banks Repeat sequence Play speed (ms)

Quick Latency Calculator

Open row policy

Closed row policy

Results

Access Sequence

Preset

opbankrow buffer

Command Timeline

PRE RAS / ACT CAS (read + transfer) CAS (write + transfer) Auto-precharge (closed row, overlapped)

What's happening

Command Log

Created for UTK COSC530 Computer Organization.