This dependency analyzer serves as a review of the types of hazards encountered during dynamic scheduling.
- Structural - two instructions want the same hardware resource in the same cycle. The only shared resource modeled here is the CDB, which can broadcast one result per cycle.
- Control - a branch hasn't resolved yet, so the instructions after it can't safely issue.
- Data (RAW) - read-after-write, a true dependency: an instruction needs a value a prior instruction hasn't produced yet.
- Data (WAR) - write-after-read, an anti-dependency: an instruction would overwrite a register an earlier instruction still needed to read. Resolved by reservation-station tag renaming, so it costs no cycles - it's reported for awareness only.
- Data (WAW) - write-after-write, an output dependency: two instructions target the same register, so only the one that issued last should ever be the one that updates the register file. Also resolved by renaming, reported for awareness only.
Types of Hazards:
Functional Unit Latencies (cycles)
Assumes enough reservation stations that issue never stalls for lack of one, and that each functional unit accepts a new instruction every cycle. The CDB is the only structural resource modeled. Branches are assumed unresolved until they execute (no prediction), so instructions after a branch stall at issue until it resolves. Registers are named F# for the floating-point file and R# for the integer/general-purpose file (used, e.g., for base addresses in loads and stores).
Instruction Sequence
| # | Op | Operands |
|---|
Created for UTK COSC530 Computer Organization.